CPU Hardware Counters
summary
CPU chips expose a PMU with cache, branch and TLB counters accessible via Linux perf but cloud VMs typically hide them so you need a metal/whole‑chip instance and to lower /proc/sys/kernel/perf_event_paranoid or run node_exporter with -collector.perf to see OS counters; node_exporter shows OS not hardware counters, cAdvisor requires building from source and Intel’s 333‑page event list hex codes to request many events. Concrete wins: 1,500 TLB entries cover ~6MB with 4KB pages, switching to transparent huge pages (2MB) cuts TLB misses and startup from ~64s to ~57s (~10%).
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chapters (13)
- 0:00CPU hardware counters intro
- 1:26What are CPU counters
- 6:31PMU and Perf subsystem
- 10:30VMs and hardware counters
- 13:19Bare metal counter access
- 17:20cAdvisor counter challenges
- 19:19TLB performance impact
- 23:39Huge pages for TLB misses
- 25:06Performance gains example
- 27:13Q&A on Windows counters
- 28:18Optimizing with counter data
- 30:24NUMA and security use cases
- 31:07Virtual PMU limitations
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