~/talk

RISC V Hypervisor Support

Talkat RISC-V Summit 2019 · 2019-12-09..12-12· [linux-and-operating-systems]

speakers

name:Alistair Francis

links:none on file

name:Anup Patel

links:none on file

resources

video:https://youtu.be/93C6CusxZ1Y

slides:none on file

summary

RISC-V hypervisor support is at v0.5 draft with QEMU patches adding 32- and 64-bit hypervisor/guest paths; the design uses a two-stage MMU and new H/VS CSRs so guests can run unmodified while the hypervisor controls guest-physical→host-physical mappings. Interrupts are injected via the HIPC SR, SBI 0.1 is emulated and SBI 0.2 work is underway. Two implementations exist: a monolithic type‑1 Xvisor (~1 MB binary, multiple VMs/VCPUs working on QEMU) and a type‑2 KVM port (patch series at v9, awaiting H-extension freeze to upstream); 32-bit guests, nested virtualization and real‑hardware bring‑up remain pending.

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