Innovation in CPU Architecture, Pushing Data from Edge to Cloud

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" summary

Alibaba presents a RISC-V product line from tiny 2-stage 2902 cores to a 12-stage, 64-bit gentian 9/10 high-performance core that hits >7 CoreMark and claims ~40% throughput gain versus leading RISC implementations. It implements a do issue out of order memory access model that issues one load and one store per cycle, a RISC‑V V-extension compatible vector engine (≈300+ GFLOPS half-precision per cluster), runs at 2.5 GHz on 12 nm, adds ~50 custom instructions, and publishes the SoC platform as open source on GitHub.

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" chapters (14)

1. 0:00Intro
2. 0:37Building the Chip Infrastructure of the Alot Era
3. 2:39The Continuously Evolving Processor Architecture
4. 3:33Ultra Low Power Architecture - Xuantie 902
5. 4:45Ultra High Performance Architecture - Xuantie910
6. 6:09Remarkable Performance
7. 6:31Compatible with RISC-V Specification
8. 6:55Extended Enhancement - RISC-V Turbo
9. 7:51Deep Superscalar Out-of-Order Pipeline
10. 9:40Instruction Fetch Unit with Hybrid Prediction
11. 10:36Dual Issue Out-of-Order Load Store Unit
12. 12:23Efficient Multi-core Interconnection
13. 13:52Al Optimized Vector Computing Engine
14. 14:15Back-End Physical Implementation