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Xvisor: Embedded Hypervisor for RISC-V

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Covers Xvisor, an open-source type-1 monolithic hypervisor for embedded systems, with focus on its RISC-V port. Describes RISC-V hypervisor extensions, the internals of Xvisor on RISC-V, and benefits such as memory footprint and runtime overheads; also notes Xvisor’s multi-architecture support (ARM, RISC-V, x86_64) and its maturity.

AI-written summary · about

  1. 0:00Western Digital
  2. 0:33Roadmap
  3. 3:54RISC-V H-Extension: Privilege Mode Changes
  4. 4:45RISC-V H-Extension: CSR changes
  5. 5:24RISC-V H-Extension Two-stage MMU
  6. 6:37RISC-V H-Extension: I/O & Interrupts
  7. 7:35What is Xvisor ?
  8. 8:56Xvisor: Traditional Classification
  9. 10:55Xvisor: Features (Contd.)
  10. 13:36Xvisor: Key Aspects (Contd.)
  11. 15:32Xvisor RISC-V: VCPU Context
  12. 16:19Xvisor RISC-V: Host Interrupts
  13. 16:57xvisor RISC-V: Context Switch
  14. 18:18xvisor RISC-V: Guest MMIO Emulation
  15. 19:05xvisor RISC-V: Guest RAM handling
  16. 20:34Xvisor RISC-V: SBI Interface
  17. 21:23xvisor RISC-V: Device tree based configuration
  18. 22:19xvisor RISC-V: Zero-copy Inter-Guest Transfer
  19. 23:28xvisor RISC-V: Code Size and Memory Usage
  20. 24:48xvisor RISC-V: Ideal for Embedded Systems
  21. 26:02xvisor RISC-V: Current State
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