Developing the RISC-V Hypervisor Extensions in QEMU
Talkat Open Source Summit Europe + Embedded Linux Conference Europe 2019 · on Monday, 2019-10-28· at 16:20· Forum 2·
summary
QEMU gains working support for the RISC-V hypervisor extension: full CSR handling including complex register swapping, RISC-V hypervisor CSRs and guest-visible VS copies, a functional two-stage MMU, interrupt injection via VSIP (no IOMMU or virtualized interrupt controller yet), and 32/64-bit support with patches on the QEMU and KVM mailing lists to enable with -cpu rv64,x-h=true. Bare‑metal Xvisor guests boot and network in the demo; nested virtualization remains untested and 32‑bit Linux guests still fail.
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chapters (19)
- 0:00Western Digital
- 0:21Overview
- 0:48What is a Hypervisor?
- 2:46RISC-V H-Extension: Spec Status
- 4:04RISC-V H-Extension. Privilege Mode Changes
- 5:36RISC-V H-Extension CSR changes
- 7:27RISC-V H-Extension Two-stage MMU
- 8:46RISC-V H-Extensions 1/0 & Interrupts
- 9:56RISC-V Hypervisor Compared to AArch64
- 10:57Current RISC-V Hypervisors
- 14:00Current QEMU Implementation
- 15:16Changes made to QEMU in preparation
- 16:23Maintaining the Hypervisor State
- 17:41Two Stage MMU
- 19:42Handling Register Swapping in QEMU
- 22:56Future Work
- 24:32Improvements proposed from QEMU work
- 25:02Overall Current Status
- 26:10Xvisor Running on QEMU Demo
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