Open ISAs (RISC-V, OpenPOWER, etc)
summary
RISC-V and OpenPOWER move from experiments to deployable stacks: RISC-V toolchains and distros (GCC/LLVM, glibc, Debian/Fedora) now boot on QEMU and silicon like SiFive U740 HiFive Unmatched, microcontroller boards and Kendryte-class 64-bit demos; three draft RISC-V extensions (vector, hypervisor, bitmanip) plus ePMP security work are near freeze. Projects only possible with open ISAs: OpenTitan uses Ibex as a 32-bit RoT built with FuseSoC, Swerv EH1 cores via LiteX/VexRiscv, and OmniXtend cache-coherent Ethernet fabric; Microwatt/Chisel and IBM A2/A2i cores exist, and Raptor’s Kestrel open BMC boots POWER9.
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chapters (27)
- 0:00Introduction
- 1:09Welcome
- 10:10Risk 5 Boards
- 11:52Fuse
- 13:27Open Titan
- 16:36Precursor
- 18:18OmniEXT
- 19:50Conclusion
- 20:35History of PowerPC
- 23:13Longevity of PowerPC
- 23:46OpenPower ISA
- 25:44Information Implementation
- 26:17Power 9 Die
- 27:21Microwave
- 29:35Chisel
- 30:14LibraStock
- 32:35A2I
- 34:22A20I
- 35:10Blackbird Talon 2
- 35:51Kestrel SoftBMC
- 37:07PowerPC Notebook
- 37:59OpenPOWER Sessions
- 38:37Stickers
- 39:08OpenPOWER Foundation
- 39:47Closing remarks
- 40:05Wrapup
- 41:23Lunch Break
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