FPGA Design with Chisel
summary
Chisel is a Scala-based HDL that generates Verilog (outputs Verilog) and brings implicit clock and reset semantics, a real type system and reusable bundle grouping of signals; it supports unit tests and CI so most verification runs in software (IntelliJ + ScalaTest) instead of flashing an FPGA. It’s production-grade (Rocket Chip, Google Edge TPU), integrates with black-box Verilog, and was used to build a MiSTer arcade core (Dodonpachi) running original ROMs on a Cyclone V D10‑Nano board; vendor tools (Quartus/Vivado) still synthesize the bitstream.
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chapters (12)
- 0:00Intro
- 0:45Welcome
- 1:25About me
- 2:33Overview
- 3:19What are FPGAs
- 5:43Why FPGAs
- 6:02Prototype FPGAs
- 9:23Vhdl
- 17:30Chisel
- 23:12Chisel Fundamentals
- 30:11MrFPGA
- 32:14Core Demo
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