Chisel 6 and beyond
summary
Chisel 6 moves the FIRRTL implementation to an MLIR-backed Circuit/ferTool pipeline for much faster, lower-memory compilation and faster feature work. New features focus on verification: linear temporal properties (SVA) emitted with reset-default behavior and stable probes/XMR via generated define files plus composable layers for bind-like verification. Source-level waveform debugging lands as an alpha with Verity/HGDD and a Surfer demo. Direct linking aims to eliminate the ~10% serialization/deserialization cost.
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chapters (13)
- 0:00Introduction
- 0:42What is Chisel
- 2:51Compiler changes
- 4:55Versioning and releases
- 5:40Chisel 6 features
- 6:43Intrinsics and advanced
- 8:28Probes and layers
- 9:53Verification collateral
- 10:56Source debugging in Verity
- 12:38Public modules and choices
- 13:44DPI support and linking
- 15:09Scala 3 support
- 15:50Q&A
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