Artifact Evaluation for the Field Programmable Gate Array Community
summary
Artifact Evaluation is established for FPGA papers: the process introduced AE to the FPGA community five years ago and now issues ACM/IEEE badges, requires a DOI (Zenodo snapshots recommended) and pairs authors with evaluators. Adoption covers major FPGA venues; typical conferences publish ~25–30 long papers and about 20–30% of long papers get evaluated. Practical hurdles include proprietary 2+ GB toolchains that resist containerization (Code Ocean), board-specific flows that break VM images, and occasional use of AWS F1 instances to reproduce results.
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chapters (7)
- 0:00Artifact evaluation for FPGAs
- 3:10Origins and purpose
- 6:46FPGA artifacts in containers
- 10:27Voluntary participation
- 13:19DOI and citation requirements
- 16:08Container limits and AWS F1
- 17:52Vendor policies and reproducibility
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