How to design your own chip?
summary
Shows concrete steps and limits: simulation with Verilator translating Verilog to C or VHDL simulators, synthesis with Yosys and Project IceStorm onto tiny ice40 FPGAs (≈40k gates) or vendor tools for bigger FPGAs (~200 MHz practical clocks). Claims tapeout money is real — multi‑project wafers cut cost but a small 40 nm run (≈50 bare dies) still approaches €50,000 and yields maybe 10–20 working parts. Open RISC/V and RISC‑V projects already run on FPGA.
AI-written summary · about
chapters (29)
- 0:00Start
- 2:49What's the difference?
- 4:11Design Entry: HDL
- 5:08The Digital Hardware Design Flow
- 10:05Simulation: Required Ingredients
- 10:32Write your code
- 13:36Testing & Verification
- 15:22"The Simulation Check": Results
- 16:13FPGA Design: Required Ingredients
- 16:30FPGA Synthesis
- 18:43FPGA Implementation
- 19:54FPGA Boards: student ( 100$)
- 20:56FPGA Boards: amateur (-500$)
- 21:50FPGA Board: pro ( 1000 $)
- 25:14ASIC Production: Required Ingredients
- 25:34The Design Kit
- 28:24ASIC Implementation
- 30:06Got Money?
- 33:39"The ASIC Check": Results
- 37:51How to live together?
- 38:10Choose a license
- 38:40Licensing Permissive
- 39:45Licensing: Weak Copyleft •File-based copyleft
- 41:06Licensing Strong Copyleft
- 44:56Introducing LibreCores
- 47:05LibreCores: Where are we today?
- 47:23Who's behind all that?
- 49:30So: How to design your own chip?
- 50:16Conference Announcement
related talks
07mFPGA and open hardware
38mOpen-Source Tools for FPGA Development
40mKeynote: Open Source FPGA Tooling
44mASICone, from Verilog to GDSII with open source tools
14mOpen Source Hardware: Hacking Silicon for Fun (instead of profit)
18mOpen source chip design: for fun and for profit
20mOpen-Source FPGAs: Tools, Flows, and Visualization
01h 18mReconfigurable Architectures: Generalities,Open-source and emerging-technologies