Philipp Wagner
where else to find them
no profile links on file
what they talk about
all 5 in the filters
where they keep going back
- ORConf3 editions2018–2023
all 4 in the filters
on a stage with
never shared a talk
who talks about the same things
- Peter Birch3 talks
- Olof Kindgren14 talks
- Karol Gugala12 talks
- Andrew Ross8 talks
- Staf Verhaegen9 talks
- Sponsor1 talk
| title | conference | date |
|---|---|---|
| Introducing Opensearch in existing multisource enterprise App | OpenSearchCon Europe 2024 | 2024-05-06 |
Case study of adding OpenSearch to an app that keeps data in Oracle DB and MongoDB without migrating: change data capture uses Debezium + Kafka CDC to stream… | ||
| How cocotb made Python-powered verification mainstream -- and what comes next | ORConf 2023 | 2023-09-15 |
cocotb now ships 250 prebuilt wheels (simulator × Python × platform) so users no longer compile C++ at install time, and CI runs publicly against Questa… | ||
| News from cocotb land | ORConf 2019 | 2019-09-27 |
cocotb now ships as a pip package so you can pip install cocotb and run Python-driven RTL tests; the project grew by 20,000 lines between long gaps and moves… | ||
| Ibex and The Mountain of Open Participation: How lowRISC lets everyone participate | Week of Open Source Hardware 2019 | 2019-06-13 |
Ibex is an RV32 two-stage core targeting ARM M0 class area and IPC, with optional I/E/M and compressed ISA and a history from Zero-Riscy. LowRISC updates… | ||
| Cocotb: Python-powered hardware verification | Week of Open Source Hardware 2019 | 2019-06-13 |
Cocotb claims that RTL verification is best written as software and provides a simulator plug‑in that links simulators to Python via VPI/FLI/VHPI. It runs on… | ||
| Find better cores with LibreCores | ORConf 2018 | 2018-09-21 |
A community site that aggregates IP cores and project metadata from GitHub and shows code activity graphs now adds a hierarchical classification, autocomplete… | ||
| Look inside your SoC with Open SoC Debug | ORConf 2018 | 2018-09-21 |
Open SoC Debug is a full spec plus reference hardware and software stack that adds tracing, memory access and UART tunneling to SoCs, with working support for… | ||
| How to design your own chip? | FrOSCon 2016 | 2016-08-20 |
Shows concrete steps and limits: simulation with Verilator translating Verilog to C or VHDL simulators, synthesis with Yosys and Project IceStorm onto tiny… | ||
| nothing matches | ||