Karol Gugala
where else to find them
what they talk about
all 7 in the filters
where they keep going back
- Latch-Up2 editions2024–2026
- ORConf2 editions2019–2023
- Zephyr Developer Summit2 editions2022–2023
all 6 in the filters
on a stage with
who talks about the same things
- Michael Gielda25 talks
- Hiroshi Tokita4 talks
- Piotr Zierhoffer3 talks
- Mohammed Billoo11 talks
- Benjamin Cabé30 talks
- Tobias Kästner11 talks
| title | conference | date |
|---|---|---|
| CHIPS Alliance: towards a unified open source ASIC design & DV workflow | Latch-Up 2026 | 2026-05-01 |
CHIPS Alliance consolidates six permissively licensed projects and shows concrete outputs: an SV-tools suite with SV-tests, Verible, Synlig and RISC‑V DV… | ||
| Open source RTL verification with Verilator | Latch-Up 2024 | 2024-04-19 |
Verilator now supports timing-aware simulation via a new coroutine scheduler and compiled UVM SystemVerilog constructs so UVM code transpiles to C++ and runs… | ||
| Warp Pipe: Library for Simulation-Driven Development of PCIe Devices... | Zephyr Developer Summit @ Embedded Open Source Summit 2024 | 2024-04-16 |
Warp Pipe is an Apache‑licensed C library that simulates PCIe networks with tight Zephyr integration and native adapters for Qemu and Renode, enabling mixed… | ||
| Warp Pipe: Library for Simulation-Driven Development of PCIe Devices... | Embedded Open Source Summit 2024 | 2024-04-16 |
Warp Pipe is an Apache-licensed C library that models PCIe as a packetized network at instruction‑level speed while preserving DLLP and TLP behavior, using… | ||
| Open Source Digital Design Tooling Updates | ORConf 2023 | 2023-09-15 |
CHIPS Alliance reports concrete tooling: an open SV Test suite runs SystemVerilog compliance across tools and shows most tests green; Verible supplies linting… | ||
| Enabling the Silicon Labs EFR Family in Zephyr – a Case Study... | Zephyr Developer Summit 2023 | 2023-06-27 |
Adds Zephyr support for the Silicon Labs EFR family with concrete outcomes: BG22 and XG24 platforms land as split, incremental PRs after resolving HAL… | ||
| Open source FPGA NVMe accelerator platform for BPF driven ML processing with Linux/... | Linux Plumbers Conference 2022 | 2022-09-12 |
An open source FPGA NVMe accelerator platform that runs Cortex‑A53 + Cortex‑R5 with Linux and Zephyr uses remoteproc/OpenAMP to pass custom NVMe commands and… | ||
| Open Source NVMe AI Accelerator Platform with Zephyr | Zephyr Developer Summit 2022 | 2022-06-07 |
An open source NVMe AI accelerator platform actually exists: Zephyr on Cortex‑R handling NVMe registers and DMA, an UltraScale+ FPGA fabric hosting a TVM/VTA… | ||
| VPR device models generation from Verilog with V2X | ORConf 2019 | 2019-09-27 |
V2X converts Verilog models into VPR architecture XML (model and pb_type) by running Yosys to JSON then Python generators that emit PB type and model files… | ||
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