Piotr Zierhoffer
where else to find them
what they talk about
where they keep going back
no series more than once — all 3 in the filters
on a stage with
- Ederson de Souzaonce
- Michael Gieldaonce
- Pete Wardenonce
who talks about the same things
- Michael Gielda25 talks
- Karol Gugala12 talks
- Hiroshi Tokita4 talks
- Mohammed Billoo11 talks
- Yasushi Shoji3 talks
- Chris Gammell6 talks
| title | conference | date |
|---|---|---|
| Automated, Simulation-Based Flow for Low-Cost FPGA-Accelerated Devices with Zeph... | Zephyr Developer Summit @ Embedded Open Source Summit 2024 | 2024-04-16 |
PolarFire SoC with 4+1 RISC‑V cores and an integrated FPGA is now usable on BeagleV‑Fire at ~$150 with a contributed Zephyr port, a Renode model and VS Code /… | ||
| Automated, Simulation-Based Flow for Low-Cost FPGA-Accelerated Devices with Z... | Embedded Open Source Summit 2024 | 2024-04-16 |
Shows a usable, automated flow that takes a visual hardware graph and produces device trees, builds Zephyr, and runs the result in Renode simulator with FPGA… | ||
| Mini-conference: RISC-V Support in Zephyr | Zephyr Developer Summit 2022 | 2022-06-07 |
Shows concrete progress and real problems: SMP merged in Zephyr v3.1 with working tests on the renode simulator, but real PolarFire silicon exposes a monitor… | ||
| nothing matches | ||