Michael Gielda
where else to find them
what they talk about
all 9 in the filters
where they keep going back
- ORConf3 editions2018–2023
- Zephyr Developer Summit2 editions2022–2023
- RISC-V Summit2 editions2019–2022
all 12 in the filters
on a stage with
- Kai Yick2×
- Allan J. Cantleonce
- Annemarie Labathonce
all 12 in the filters
who talks about the same things
- Karol Gugala12 talks
- Piotr Zierhoffer3 talks
- Benjamin Cabé30 talks
- Hiroshi Tokita4 talks
- Drew Fustini21 talks
- Tobias Kästner11 talks
| title | conference | date |
|---|---|---|
| Generate, Develop and Visualize Zephyr Platforms and Apps with Visual System Desig... | Zephyr Developer Summit @ Embedded Open Source Summit 2024 | 2024-04-16 |
An end-to-end open source flow ties Visual System Designer to Renode and Zephyr to generate device trees, platform descriptions and test binaries… | ||
| Generate, Develop and Visualize Zephyr Platforms and Apps with Visual System Desi... | Embedded Open Source Summit 2024 | 2024-04-16 |
An end to end flow converts diagrammed hardware into Zephyr platform files, generating device tree generation and board files plus test binaries from a Visual… | ||
| Open Sourcing Project Sparrow | RISC-V Summit North America 2023 | 2023-11-06 |
Project Open Secura (formerly Sparrow) is an open‑source RISC‑V secure ML system: a configurable SoC reference design with an open IP library, custom RISC‑V… | ||
| Caliptra: Building Open Source Security IP with Open Source Tools | ORConf 2023 | 2023-09-15 |
Caliptra is an open-source root of trust developed jointly by Nvidia, Google, Microsoft and AMD and targets a near-term 1.0 RTL release intended for real-world… | ||
| Renode - open source systems simulation framework | ORConf 2023 | 2023-09-15 |
Renode is an open‑source simulator that runs 280 real boards in simulation, models RISC‑V (including vectors and custom instructions) and ARM Cortex A/R 32/64… | ||
| Hardware: a messy landscape we all love | ORConf 2023 | 2023-09-15 |
A public Open Hardware Portal hosts dozens of open-source KiCad designs (permissive license) including FPGA, Nvidia and Snapdragon boards and supplies KiCad… | ||
| Keynote: Organising the Hardware Ecosystem with Open Source: Antmicro's Visual... | Zephyr Developer Summit 2023 | 2023-06-27 |
A Visual System Designer builds block diagrams from a curated library and generates device tree → Renode config so compiled Zephyr or Linux firmware runs in… | ||
| RISC-V and Antmicro’s visual system designer: Everything everywhere all at once | RISC-V Summit Europe 2023 | 2023-06-05 |
A visual system designer ties an open-component database, Renode simulator and Kenning + IREE ML toolchain to let users assemble RISC‑V cores, peripherals… | ||
| HW-SW Co-development for RISC-V Based Secure ML Systems with the Sparro... | RISC-V Summit 2022 | 2022-12-13 |
Sparrow builds a low‑power RISC‑V ambient ML platform using Renode for full-system, pre‑silicon co‑development and targets OpenTitan roots of trust including… | ||
| Renode’s Zephyr Dashboard: Simulating 130+ Zephyr Platforms | Zephyr Developer Summit 2022 | 2022-06-07 |
Renode’s Zephyr Dashboard claims simulating 170+ Zephyr platforms by translating Zephyr device trees into Renode platform descriptions with a tool called… | ||
| Mini-conference: RISC-V Support in Zephyr | Zephyr Developer Summit 2022 | 2022-06-07 |
Shows concrete progress and real problems: SMP merged in Zephyr v3.1 with working tests on the renode simulator, but real PolarFire silicon exposes a monitor… | ||
| Keynote: From Zephyr’s Structured Data to Traceable and Testable Open Hardware | Zephyr Developer Summit 2022 | 2022-06-07 |
Zephyr’s device-tree data drives a reproducible pipeline: west build produces binaries that run in the Renode simulator, an interactive CI dashboard compiles… | ||
| Unlocking Open Source RISC-V SoC Verification | Spring 2022 RISC-V Week — RISC-V International Day | 2022-05-05 |
CHIPS Alliance integrates Verilator changes so Verilator 5.x can run event‑driven SystemVerilog testbenches by adding dynamic scheduling (first done as a… | ||
| Software-driven Hardware in the Data Center: LibreBMC, Renode, RowHammer... | OpenPOWER Summit NA 2021 | 2021-10-28 |
Open source FPGA BMC implemented as a LibreBMC FPGA dcscm module runs Zephyr or Linux, supports external TPMs and migrates between Artix7 and ECP5 with full… | ||
| Welcome & Keynote Sessions | OpenPOWER Summit NA 2020 | 2020-09-15 |
OpenPower announces a liberalized ISA and shows working open cores and toolchains: Microwatt proof‑of‑concept runs after weeks, IBM contributes the A2I/A2O… | ||
| Fomu Python, RISC V, and FPGA in your USB Port | RISC-V Summit 2019 | 2019-12-09 |
Fomu is a USB-stick FPGA that implements a RISC-V core and actually works: a Lattice iCE40 UP5K with ~5000 LUTs, 128 KB single‑port RAM, ≈2 MB flash, one RGB… | ||
| Renode coming to a cloud near you | ORConf 2019 | 2019-09-27 |
Renode 1.8 adds multi-core GDB support, Verilator co-simulation and an Etherbone FPGA bridge so most of a SoC runs fast in the simulator while one IP runs in… | ||
| Complex system simulation and HW/SW co-design with Renode open source simulation framework | Week of Open Source Hardware 2019 | 2019-06-13 |
Renode is an open-source, ISS-based simulator and modular framework that runs unmodified OS and embedded images, adds Python scripting and co-simulation with… | ||
| RISC-V ecosystem update | ORConf 2018 | 2018-09-21 |
RISC-V now runs 64-bit Linux in mainline Linux 4.19, has growing Zephyr support and active LLVM/GCC work, and playable FPGA hardware like the GreenWaves GAP8… | ||
| RISC-V & Renode: towards software-driven development | ORConf 2018 | 2018-09-21 |
Renode is an open-source framework that runs binary-compatible RISC-V and other SoC images, enabling multi-node simulation (demo: six virtual machines, HiFive… | ||
| Simulating Heterogeneous Multi-node 32-bit and 64-bit RISC-V Systems Running Linux and Zephyr | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Renode simulates a heterogeneous four-node setup with mixed 32‑bit and 64‑bit RISC‑V cores running Linux and Zephyr concurrently, boots two Linux instances in… | ||
| Renode: A Flexible, Open Source Simulation Framework For Building Scalable, Well Tested... | 7th RISC-V Workshop 2017 | 2017-11-28 |
Renode is an open source simulator that emulates full SoCs so teams run production binaries without a separate simulator build and simulate multiple nodes in… | ||
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