Keynote: From Zephyr’s Structured Data to Traceable and Testable Open Hardware
summary
Zephyr’s device-tree data drives a reproducible pipeline: west build produces binaries that run in the Renode simulator, an interactive CI dashboard compiles and executes five binaries across 170 different hardware boards in simulation, and artifacts (SBoM, traces, robot logs) and a web "pedia" let teams inspect memory maps, peripherals, supported drivers and prebuilt demos. The project automates binary generation, cloud Colab/GCP execution, and chip/PCB visualization so hardware choices become measurable and testable.
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chapters (13)
- 0:00Intro
- 1:23HOW TO DEAL WITH UNCERTAINTY
- 2:23FINDING YOUR WAY AROUND HARDWARE
- 3:15ZEPHYR AS AN UNIQUE SOLUTION
- 4:41WHAT ZEPHYR ENABLES
- 6:38RENODEPEDIA-MOTIVATION
- 9:17ENABLING APPLICATION DEVELOPMENT
- 11:54ARTIFACTS
- 12:29RUNTIME DATA
- 12:48EXPLORING SOC DATA
- 14:02AUTOMATED SOC MODEL GENERATION
- 16:31SUMMARY: SW-FIRST DEVELOPMENT
- 17:32ACTION ITEMS
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