Mini-conference: RISC-V Support in Zephyr
summary
Shows concrete progress and real problems: SMP merged in Zephyr v3.1 with working tests on the renode simulator, but real PolarFire silicon exposes a monitor core missing atomics that causes hangs when threads run there; toolchain issues crop up when prebuilt SDK binaries assume unsupported instructions. Machine learning work proves useful end-to-end: CFU playground on FPGA and TensorFlow Lite Micro integrate with Zephyr CI so examples run reliably, FOMO tiny FPGA boards boot, yet configurability and per‑platform profiles remain unfinished and demand rebuilding toolchains or emulator workarounds.
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chapters (7)
- 0:00Welcome to RISC-V Zephyr
- 2:08SMP on RISC-V in Zephyr
- 19:12Big RISC-V platforms Zephyr Linux
- 21:18ML on RISC-V with Zephyr
- 49:08RISC-V configurability in Zephyr
- 1:06:51Dynamic hardware in Zephyr RISC-V
- 1:15:25Summary RISC-V in Zephyr
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