Generate, Develop and Visualize Zephyr Platforms and Apps with Visual System Desi...
summary
An end to end flow converts diagrammed hardware into Zephyr platform files, generating device tree generation and board files plus test binaries from a Visual System Designer diagram, then launches those binaries in live Renode simulation. The CI-backed dashboard already covers about 470 targets (~75% of Zephyr) and the demo shows a compiled binary driving blinking LEDs and live UART/temperature values in the simulator. The portal, component library and Renodepedia are open source and due for public release soon but remain early and rough around the edges.
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chapters (9)
- 0:00Visual System Designer intro
- 2:31Modern embedded challenges
- 5:41Zephyr for hardware complexity
- 8:32Renode & Zephyr Dashboard
- 13:26Hardware data model consistency
- 15:35Visual System Designer tool
- 24:20Live demo of Visual System Designer
- 31:48Future release timeline
- 33:12Q&A
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