Debugging Heterogenous SoC Using OpenOCD
summary
OpenOCD runs on the SoC’s A53 to debug R5 and M4 cores over the on‑chip debug fabric, eliminating the need for an external JTAG dongle and delivering processor‑speed register access that surprised the authors. The implementation uses self-hosted OpenOCD on A53, direct AP accesses for M4 and an emulated AP for R5 (about 100–200 lines of state‑machine code), is merged upstream, works on AM625/TDA4VM, and leaves trace/ETM support as future work.
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chapters (18)
- 0:00OpenOCD for heterogeneous SoCs
- 3:15Standardizing MCU debugging
- 5:28Heterogeneous processor systems
- 8:15JTAG and CoreSight basics
- 10:24OpenOCD architecture
- 13:59Removing JTAG hardware
- 16:29Building OpenOCD for SoCs
- 19:37Debugging heterogeneous cores
- 21:43Remote debugging over sockets
- 23:27OpenOCD with dev tools
- 25:56Memory-based debugging benefits
- 26:18Debugging pitfalls
- 28:03Debug bypass and emulation
- 30:35OpenOCD memory mapping
- 33:27OpenOCD future directions
- 36:35RISC-V and UCI challenges
- 38:01Community resources
- 39:11Q&A
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