Latch-Up 2026
who it's for
open-source silicon engineers, verification engineers, FPGA designers, EDA tool developers, SoC architects, hardware design educators, register and RTL library authors
topics
FuseSoC and SiliconCompiler integration; Verilator four-state and UVM compatibility; open-source tapeout workflows; FPGA prototyping to ASIC mapping; waveform viewers and VCP integration; RISC-V SoC with MRAM and vector extensions; OpenROAD and agent-driven flows; analog IC layout reward functions; GDSFactory for photonics and MEMS; Python hardware modelling languages (Spade, Zuspec); PeakRDL-PyRAL register abstraction layer; open PDKs and IHP foundry progress
| title | author | length |
|---|---|---|
| Opening | Olof Shingden | 13m |
Two-day conference plus a one-day unconference with a tiny tapeout workshop on Sunday and self-organized breakout groups; Saturday evening hosts 2-minute… | ||
| Unifying FuseSoC and SiliconCompiler | Duncan Parke | 21m |
Prototype called Silisoc maps FuseSoC EDAM YAML into SiliconCompiler’s JSON schema and runs FuseSoC CLI commands against the SiliconCompiler scheduler… | ||
| FuseSoC for large real-world code bases | Olof Kindgren | 16m |
FuseSoC is a 15‑year package manager that already catalogs over a thousand public cores and scales to company repos with thousands more (one example is ~3,000… | ||
| Erbium SOC, Architecture, Design and Verification | Vijayvithal Someracharya Jahagirdar | 19m |
Erbium is a taped‑out, open‑source 8C16T RISC-V SOC with Vector and Tensor extensions, a per‑core L1 scratchpad and 16 MB MRAM, aimed at EdgeAI; the project… | ||
| CHIPS Alliance: towards a unified open source ASIC design & DV workflow | Karol Gugala | 20m |
CHIPS Alliance consolidates six permissively licensed projects and shows concrete outputs: an SV-tools suite with SV-tests, Verible, Synlig and RISC‑V DV… | ||
| Chipathon: Democratizing IC Design - A Global Open-Source Silicon Challenge | Mehdi Saligane | 22m |
Chipathon runs a multi-month IC design competition that actually delivers silicon: initial runs (61 submissions → 18 selected → 11 taped out in 2021; 54 → 22 →… | ||
| One Demoboard, Many Breakouts: Bridging FPGA Prototyping and Open-Source ASIC Tapeout | Pat Deegan | 15m |
A tiny FPGA breakout called FabricFox plugs into the TinyTapeout demoboard and runs the same pinout and APIs as the ASIC breakouts, letting designs move from… | ||
| Sustainable open silicon communities | Frans Skarman | 13m |
Surfer is a waveform viewer that ships a waveform control protocol (VCP) enabling remote control from editors and tools, which powers a GDB‑like JPDB workflow… | ||
| Strengthening Engineering Curriculum and Opportunities for Undergraduate Students | Vraj Prajapati | 22m |
University of Toronto ASIC Team builds undergraduate pathways to real silicon by using the Free and Open Source Silicon ecosystem and open toolchains like… | ||
| Verilator Update Potpourri | Todd Strader | 17m |
Hudson River Trading reports concrete Verilator changes: tracing flag produced ~50% more generated C++ so builds split into no-trace for CI and trace for… | ||
| Next big step for Verilator: towards four-state logic and UVM compatibility | Krzysztof Bieganski | 22m |
UVM 2017 and UVM 2020 compile with Verilator and nearly 100 pull requests land for scheduling (eager triggers, three‑stage scheduling, immediate finish)… | ||
| Vaporview - 2026 updates | Lloyd Ramseyer | 20m |
Vaporview is a VS Code waveform viewer that now uses a WebAssembly parser, a refreshed renderer and an extension API for interoperability with tools like Slang… | ||
| Mr. Scrub: An Open-Source, Internal Scrubber for UltraScale FPGAs | Graeme Smecher | 22m |
An open-source internal scrubber for AMD UltraScale (Kintex UltraScale 60) reads and writes configuration frames via ICAP, decodes the vendor’s interleaved… | ||
| Simulating Partial Reconfiguration in cocotb via Multi-Process DPI Barriers | Chaitanya Sharma | 17m |
Claims a working multi-process per-module simulator that lets cocotb and Verilator run a full RTL sim while swapping modules at runtime without recompilation… | ||
| Open-Source FPGAs: Tools, Flows, and Visualization | Alex Singer | 20m |
Open-source flows like VTR, OpenFPGA, and Zero ASIC's Logik let teams go from architecture spec to bitstream and even GDS or silicon proof in weeks or days… | ||
| RISC-V in Space (The Canadian version) | Mike Thompson | 25m |
An open-source RISC-V microcontroller is fabricated into silicon, radiation-hardened with a University of Saskatchewan process tweak that keeps cell geometry… | ||
| Post-Efabless Silicon on SkyWater, GlobalFoundries, and IHP | Tim Edwards | 19m |
Five chips are submitted to Cadence’s first Sky130 shuttle to recover tapeouts lost after Efabless shuts down, then designs are ported to GF180MCU on… | ||
| Full Custom - Drawing Transistors The Hard Way | Nanik Adnani | 19m |
Covers full‑custom analog layout with concrete, usable rules: five layout rules (avoid long aspect ratios, use dummy devices, interleave for matching… | ||
| Substrate: Designing Highly Configurable Analog and Mixed-Signal Circuit Generators | Rahul Kumar | 17m |
Open-source framework Substrate generates schematic and GDS from parameterized Rust code and claims process-portable generators for Skywater 130nm and Intel… | ||
| From Tapeouts to Products: Why Open-Source Silicon Must Solve Real Problems to Survive | M. Kassem | 26m |
Argument: open-source silicon survives only when it ships in real products with product-grade constraints and revenue. Claims include that the toolchain is… | ||
| A Multi-Objective Reward Function for Analog IC Layout Optimization | Eli Ferrara | 22m |
CLARA encodes layout quality as a multi-objective reward over seven metrics: four objectives (symmetry, compactness, connectivity, device grouping) and three… | ||
| From Open PDKs to Silicon: Progress at IHP | Frank Vater | 18m |
IHP publishes usable open PDKs with analog/RF features (BiCMOS G2: Ft/Fmax ~350–450 GHz) plus an upcoming CMOS 5L MPW run starting mid‑July; initial digital… | ||
| OpenROAD and the Era of Agents | Andrew Kahng | 23m |
OpenROAD becomes an experimental substrate where agents edit code, tune flows, and run closed-loop R&D: OpenROAD hosts repo-scale agents like Autopeda that… | ||
| Running an Open Source LLM on Open Source Hardware | Ethan Sifferman | 23m |
A UC Santa Cruz project builds an 1.58-bit accelerator that compiles a full transformer inference pass to an instruction stream and runs on custom functional… | ||
| Bluespec FSM: The Hidden Gem | Michael Jaggers | 21m |
Bluespec makes FSMs readable and compact by treating sequencing and guarded atomic actions as primitives, compiling to readable Verilog and offering a… | ||
| PeakRDL-PyRAL: A scalable, low-overhead Python register abstraction layer | Alex Mykyta | 18m |
PeakRDL PyRAL generates a database-backed RAL instead of massive generated Python, claims O(1) import and construction and demonstrates interactive use with… | ||
| Modeling Hardware in Python with Zuspec | Matthew Ballance | 15m |
Zuspec is a Python-native hardware modeling language that claims a single source can be progressively lowered from high‑level declarative constraints to… | ||
| Five years of Spade - A modern Hardware description language | Frans Skarman | 21m |
Spade reaches five years with concrete wins: genif metaprogramming plus lambdas enable compile‑time codegen and array maps, traits and operator overloading add… | ||
| GDSFactory: Open-Source EDA for Photonics, Quantum, MEMS, and RF Chip Design | Rishabh Iyer | 21m |
Open-source Python EDA GDSFactory claims to unify parametric PDKs, layout, FDTD and circuit simulation with plugins for ANSYS and Synopsys and reports over 2… | ||
| Lightning Talks | Carl Phillips | 22m |
Open source header that layers on the C++ event system for hardware verification and provides a concrete callback API: you post typed events, register filter… | ||
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