Bluespec FSM: The Hidden Gem
summary
Bluespec makes FSMs readable and compact by treating sequencing and guarded atomic actions as primitives, compiling to readable Verilog and offering a Bluespec-Verilog bridge for SystemVerilog users. A complex MRAM reference-trim statechart that took thousands of lines in SystemVerilog becomes a few rule-based blocks and ships in silicon; an FPGA microsecond DRAM timing controller is implemented as a clear state sequence. Tooling includes a Haskell-based compiler, an open-source AXI library, and an active community for support.
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chapters (7)
- 0:00Introduction to Bluespec FSMs
- 1:28What is HDL and Bluespec
- 3:54Why Bluespec beats Verilog
- 8:13Finite state machines in Bluespec
- 10:00Real-world Bluespec FSMs
- 12:26Unique Bluespec FSMs
- 13:11Q&A
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