Modeling Hardware in Python with Zuspec
summary
Zuspec is a Python-native hardware modeling language that claims a single source can be progressively lowered from high‑level declarative constraints to synthesizable Verilog. Prototype tooling produces synthesizable Verilog and a faster C model, evaluates models statistically, and simulates at native speed. It uses an IR that preserves transforms back into Python, exposes resource annotations like share and lock to guide scheduling, and supports adding pipelining/retiming by layering intent rather than rewriting RTL. Results are early but working.
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chapters (8)
- 0:00Introduction
- 1:03Traditional RTL challenges
- 2:51Zuspec and Python approach
- 4:59RISC-V core example
- 7:50Constraints for synthesis
- 8:53Full design in Python
- 10:37Zuspec benefits
- 12:03Q&A
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