A Multi-Objective Reward Function for Analog IC Layout Optimization
summary
CLARA encodes layout quality as a multi-objective reward over seven metrics: four objectives (symmetry, compactness, connectivity, device grouping) and three costs (overlap, bounds, spacing). Optimization uses simulated annealing with gradient-descent-style selection (5,000 random perturbations per step, ~80 steps) and graduated penalties that give dense feedback. Validation on three SKY130 circuits shows convergence from massive overlaps to feasible layouts with grouping driving trade-offs; RL training struggles from data scarcity and outputs need human DRC fixes.
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chapters (19)
- 0:00Analog IC layout research
- 1:22Key heuristics for layout design
- 2:46Reinforcement learning loop
- 3:50Brute-force vs RL approaches
- 4:53Multi-objective reward function
- 7:18Cost metrics and penalties
- 8:22Reward validation with annealing
- 9:48Reward evolution during training
- 11:53RL model challenges
- 12:35Data scarcity in analog design
- 13:18Key takeaways and future
- 14:07Q&A: DRC issues
- 15:11Q&A: Human intervention role
- 15:53Q&A: Action space modeling
- 16:55Q&A: DRC check passes
- 17:56Q&A: Reward function for training
- 19:40Q&A: Expanding training data
- 20:41Q&A: Physics vs heuristic
- 21:45Q&A: Physics simulation cost
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