Hardware DSLs
summary
Claims that domain-specific hardware DSLs let one write a single high-level spec that automatically produces simulator, RTL and SMT verification models and even an assembler and code generator. Uses Python-embedded DSLs (magma, chisel-style ideas), text templating (mako), and a stack of tools to target an actual coarse-grain reconfigurable array; two tapeouts are complete and the second tapeout works. Shows a 100,000× energy-efficiency gap motivating domain-specific accelerators and uses Peak, Lake, Canal to build the chip.
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chapters (13)
- 0:00Introduction
- 1:25Motivation for hardware DSLs
- 10:30Hardware design languages
- 21:46Partial evaluation for hardware
- 28:24Domain-specific languages for hardware
- 33:16Building specialized hardware
- 37:26Peak DSL for processors
- 47:20Benefits of single specification
- 51:31Future of hardware languages
- 54:22Q&A: hardware DSLs and quantum computing
- 1:00:48Q&A: dependent types and Python
- 1:06:23Q&A: shared elements in hardware DSLs
- 1:09:22Closing remarks
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