DRAM simulation with the simulator DRAMSys
summary
DRAMSys is an open-source SystemC TLM-2.0 framework with commercial models for DDR5/LPDDR5/HBM3 and academic free licenses, claiming 400x speedup versus RTL while keeping cycle-accurate results by using an event-reducing custom TLM protocol and asynchronous transaction modeling. A DM-ML DSL (timed Petri net semantics) generates SystemC sources and SVA checks, cutting DDR5 model time to about two weeks. Bundled tools include a trace analyzer, power/thermal/error models, and RTL integration via transactors.
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chapters (6)
- 0:00Introduction to DRAMSys
- 1:31DRAM architecture basics
- 2:16Simulation and modeling
- 6:11Formalizing DRAM standards
- 9:24Analysis and tools
- 10:19Q&A and closing remarks
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