Switchboard: Calling All Hardware Models

on YouTube ↗16m

" summary

Switchboard wires RTL, FPGA, C++ and Python models via simple 52-byte packet messages over mmap-backed shared-memory queues that present a ready/valid, single-producer single-consumer channel. Each link hits up to 1 GB/s / 200 ns latency in practice, exposing queues as named files so RTL on simulators or F1 cloud FPGAs and software all talk the same protocol. Built-in adapters include axi and Umi; Zero ASIC runs it to boot Linux and run ML models near realtime.

AI-written summary · about

" chapters (7)

1. 0:00Switchboard framework intro
2. 2:09Switchboard architecture
3. 7:02Python and RTL example
4. 9:30High-level interfaces like AXI
5. 12:03Mix-signal simulation
6. 13:30Performance and demos
7. 14:33Q&A on QEMU, FPGA, Wishbone

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