Open-source resources for learning the Bluespec HL-HDLs
summary
Free, open-source course materials accompany a new ~300‑page textbook and a single GitHub repo with PDFs, sources, Makefiles and testbenches; materials teach Bluespec HL-HDLs plus RISC‑V by building two runnable CPUs: Drum (FSM‑sequenced single‑cycle) and a pipelined RISC‑V core. Flow compiles BSV via the BSC -> Verilator -> AWS F1 path to Verilog, runs stage‑by‑stage traces and CSV pipeline visualizations, enforces static bit‑width and clock‑domain checks, and uses atomic‑transaction semantics to simplify concurrent state updates.
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chapters (9)
- 0:00Introduction
- 1:45Bluespec HL-HDL features
- 3:51Language design inspirations
- 8:07Compiler history and status
- 8:30New textbook and materials
- 11:22Book structure and approach
- 13:25Debugging and optimization
- 14:28Key takeaways and resources
- 15:31Q&A
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