CedarEDA for open source silicon
summary
A Julia-written analog simulator and optimizer compiles spice and Verilog into a common IR and generates JIT machine code for CPU (GPU planned) and claims performance competitive with commercial tools while noting current compile latency on some workloads. It auto-installs PDKs via the Julia package manager and ships with Sky130 and GF180 support, a cloud GUI and batch/CICD APIs, has built-in differentiability and ML hooks, and publishes almost all source under CERN OHL (experiment) on GitHub with paid commercial licenses for proprietary PDK use.
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chapters (8)
- 0:00Introduction
- 1:11About Cedar
- 4:44Architecture
- 9:30Cloud
- 10:52Licensing
- 11:46Special Announcement
- 15:34Demo
- 18:35QA
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