PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface
summary
PyHDL-IF provides an object-oriented Python↔HDL bridge that is 99% pure-Python with a tiny precompiled C++ bootstrap, avoiding per-user generated wrappers. It generates a pure SystemVerilog wrapper from annotated Python classes so SystemVerilog can call Python export functions and tasks (example: a count ones example where an SV method returns a Python-calculated integer). The library synchronizes Python async coroutines with SystemVerilog threads, integrates with cocotb when present, and is alpha-quality with working examples and a roadmap.
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chapters (7)
- 0:00Introduction
- 1:45Python-HDL interoperability
- 3:52PyHDL-IF library architecture
- 5:19Reference algorithms with Python-HDL
- 8:35UVM sequences in Python
- 11:50Library features overview
- 12:54Q&A
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