Python as a language for testing and code generation
summary
Describes using Python to generate parameterised VHDL, run file‑based unit tests and drive FPGA validation, noting generation replaces unsupported VHDL recursion and tedious wrappers. Uses FuseSoC with fusesoc_generators to call memory compilers for many width/depth combos, VUnit plus file IO for simulator tests, and FPGA-hosted Axi4Lite tests via axilent; automatic SLV conversion via slvcodec generates converters and testbenches and the setup proves reliable for long FPGA runs.
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