Retargeting a legacy ISA CPU core to the RISC-V architecture

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" summary

Describes retargeting a proprietary 6-stage legacy ISA CPU core to the RISC‑V ISA: two BSc apprentices at ChipCraft evaluated feasibility and implemented most of the User-Level ISA and parts of the Privileged Architecture over a three‑month apprenticeship. Notes ongoing work toward full RISC‑V compliance and plans to develop a low‑power single‑stage RISC‑V twin core to be released under the GPL.

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" chapters (8)

1. 0:00Intro
2. 0:19Outline
3. 0:55Background
4. 1:47Experience (0)
5. 3:31Chip Craft Sp. z o.o.
6. 5:09CPU Retargeting (1)
7. 7:03riscy-tests results
8. 7:58Future work

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