Rishiyur Nikhil
where else to find them
what they talk about
where they keep going back
no series more than once — all 5 in the filters
on a stage with
- Niraj Sharmaonce
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Open-source resources for learning the Bluespec HL-HDLs | Latch-Up 2024 | 2024-04-19 |
Free, open-source course materials accompany a new ~300‑page textbook and a single GitHub repo with PDFs, sources, Makefiles and testbenches; materials teach… | ||
| A Tour of the RISC V ISA Formal Specification | RISC-V Summit 2019 | 2019-12-09 |
The RISC‑V ISA is encoded in the Sail language as executable, strongly typed AST + encode/decode + execute + assembly clauses and the team produces OCaml/C… | ||
| Formal Specification of the RISC-V Instruction Set Architecture | RISC-V Workshop Chennai 2018 | 2018-07-18 |
An executable, machine‑readable RISC‑V ISA is implemented as an elementary Haskell executable spec that defines one‑instruction‑at‑a‑time semantics with… | ||
| The RISC-V Formal Specification Technical Group: Progress Report | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Working group of about 10–15 regular members produces a machine-readable ISA semantics implemented in Haskell (MIT variant) that runs ELF/memory images as an… | ||
| ISA Formal Task Group Update | 7th RISC-V Workshop 2017 | 2017-11-28 |
A machine-readable formal ISA specification is written in a simple functional notation using a Haskell syntax subset, with an algebraic AST, a 32-bit decode… | ||
| nothing matches | ||