RISC-V Workshop Chennai 2018
2018-07-18..2018-07-19
Chennai, India
| title | author | length |
|---|---|---|
| RISC-V ISA & Foundation Overview | Rick O'Connor | 21m |
RISC‑V claims a simple, modular ISA that scales from teaching to production: the base RV32I base <50 instructions plus standard extensions like M, A, F, D and… | ||
| RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance | Gnanasekar Rajakumar, Ravikumar Gaddam | 18m |
Presentations by Gnanasekar Rajakumar and Ravikumar Gaddam at Western Digital on July 18, 2018 at the RISC-V Workshop in Chennai, hosted by the Indian… | ||
| Going Beyond the RISC-V General Purpose Solutions | Neel Gala | 27m |
Presentation by Neel Gala at InCore Semiconductors on July 18, 2018 at the RISC-V Workshop in Chennai, hosted by the Indian Institute of Technology Madras in… | ||
| Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72 | Karthikeyan Sugymaran, Tom Jose | 24m |
Presentations by Karthikeyan Sugymaran and Tom Jose at Mirabilis Design on July 18, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of… | ||
| It’s Not About the Core, It’s About the System | Gajinder Panesar | 39m |
Provides a silicon IP suite that adds an orthogonal, non‑intrusive monitoring plane: runtime‑configurable bus monitors, status monitors, trace receivers and a… | ||
| RiTA: RISC-V Trace Analyzer | Anmol Sahoo, Neel Gala | 10m |
Presentations by Anmol Sahoo at IIT Madras and Neel Gala at InCore Semiconductors on July 18, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian… | ||
| KEYNOTE: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures | Vivek Tyagi | 24m |
Western Digital commits its storage business to RISC‑V and builds a first SoC around an RV32IMC core (2‑way superscalar, nine‑stage pipeline) intended as a… | ||
| Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms | Huzefa Cutlerywala | 29m |
SiFive presents concrete results: two RISC-V platforms—Freedom Everywhere (FE310 microcontroller, sold over 1,000 boards) and Freedom Unleashed (FU540 quad U54… | ||
| Mi-V RISC-V Embedded Ecosystem | Krishnakumar Ranamoorthi | 17m |
Mi-V ecosystem packages RISC-V soft cores, an Eclipse-based SoftConsole toolchain (also supports ARM), and evaluation boards including a $99 FPGA dev board… | ||
| Verification of the PULPino SoC Platform Using UVM | Mahesh R, Shamanth HK | 13m |
Presentations by Mahesh R and Shamanth HK at Cisma Consultants on July 18, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of Technology… | ||
| Porting Graphical Stacks to RISC-V using QEMU and Yocto | Atish Patra | 11m |
Port of Plasma Mobile to RISC‑V using QEMU virt and Yocto layers builds a full graphical stack: Linux kernel guest, meta-riscv plus meta-qt5 and KDE… | ||
| Panel: Evolving a RISC-V Based Ecosystem in India | Vivek Tyagi, Konala Varma, Mahesha Nanjundaiah, Asutosh Upadhyay, Amudhan Balasubramanian, G S Madhusudan | 01h 08m |
Panel includes Vivek Tyagi at Western Digital, Konala Varma at Intel, Mahesha Nanjundaiah at HPE and Asutosh Upadhyay at Axilor Ventures, Amudhan… | ||
| Poster/Demo Previews | Andrea Bocco, Tiago Trevian Jost, Shubhodeep Roy Choudhury, Kevin McDermott, Atish Patra, Gajinder Panesar | 17m |
A verification package called Sting test generator produces many randomized configurations per test, runs on simulation, emulation, FPGA and silicon, and finds… | ||
| Linux Kernel on RISC-V: Where Do We Stand | Atish Patra, Damien Le Moal | 32m |
Linux on RISC‑V already has upstream binutils (Mar 2017), GCC (May 2017), initial kernel patches (Nov 2017), QEMU support (Mar 2018) and distro ports (Debian… | ||
| A Comprehensive Framework For Power-Based Side-Channel Leakage Evaluation of SHAKTI C-Class | Muhammad Arsath, Chester Rebeiro | 21m |
Presentations by Muhammad Arsath and Chester Rebeiro at IIT Madras on July 19, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of… | ||
| Shakti M-Class Libre RISC-V SoC | Luke Kenneth Casson Leighton | 30m |
A 2.5 GHz RISC-V 64-bit SoC design targets a mobile-class chip with an embedded 3D GPU with 1080p decode, aiming for no backdoor coprocessors and sovereignty… | ||
| SLSV: The Shakti LockStep Verification Framework | Paul George, Lavanya Jagan | 27m |
Presentation by Paul George and Lavanya Jagan at IIT Madras on July 19, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of Technology… | ||
| A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA) | Kunal Ghosh, Anagha Ghosh | 41m |
Survey shows a practical floor‑planning method that breaks the E31 core into hierarchical subblocks, runs synthesis with Yosys, placement with… | ||
| Integrating Gen-Z in Server-Class RISC-V Processors | Mohan Parthasarathy | 30m |
Gen Z is a memory-semantic fabric that exposes load/store access to remote memory, ships 16–212 Giga-transactions/sec and 32–400+ GB/s per module, and scales… | ||
| Formal Specification of the RISC-V Instruction Set Architecture | Rishiyur Nikhil, Niraj Sharma | 32m |
An executable, machine‑readable RISC‑V ISA is implemented as an elementary Haskell executable spec that defines one‑instruction‑at‑a‑time semantics with… | ||
| RISC-V Workshop Chennai Conclusion | Rick O'Connor | 05m |
Presentation by Rick O’Connor at RISC-V Foundation on July 19, 2018 at the RISC-V Workshop in Chennai, hosted by The Indian Institute of Technology Madras in… | ||
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