Luke Kenneth Casson Leighton
where else to find them
no profile links on file
what they talk about
all 4 in the filters
where they keep going back
- FOSDEM2 editions2021–2022
- OpenPOWER Summit NA2 editions2020–2021
all 4 in the filters
on a stage with
all 38 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| The Libre-SOC Project | FOSDEM 2022 | 2022-02-05 |
a status update for the OpenPOWER Libre-SOC core: booting linux
The Libre-SOC Project aims to develop a family of OpenPOWER processors, ultimately working… | ||
| nMigen HDL | FOSDEM 2022 | 2022-02-05 |
a way to create hardware in python
nmigen™ is a tool for creating hardware, whether for ASICs or for FPGAs. it is not itself an actual language (like Verilog… | ||
| Draft SVP64 in-place Matrix Multiply and FFT / DCT | OpenPOWER Summit NA 2021 | 2021-10-28 |
Claims an SVP64 prefix extension that runs in-place matrix multiply up to 128 FMACs with only a 3-instruction hot loop (shape setup, remap, FMAC), removing the… | ||
| The LibreSOC Project | FOSDEM 2021 | 2021-02-06 |
a hybrid 3D CPU / VPU / GPU based on OpenPOWER
The LibreSOC Project is a hybrid 3D CPU, GPU and VPU, designed for use in mass-volume products such as… | ||
| The LibreSOC Project: Simple-V Vectorisation | FOSDEM 2021 | 2021-02-06 |
why we decided to invent a new Vector system on top of OpenPOWER
The LibreSOC hybrid 3D CPU-VPU-GPU is intended to provide a significant reduction in both… | ||
| Alliance / Coriolis2 | FOSDEM 2021 | 2021-02-06 |
parametric programmatic ASIC Place and Route using python
Coriolis is a suite of software for taking chip designs and turning them into ASICs (aka VLSI… | ||
| The LibreSOC Initiative: A hybrid CPU/VPU/GPU | OpenPOWER Summit NA 2020 | 2020-09-15 |
LibreSOC builds a single-chip hybrid CPU/VPU/GPU by adding Simple‑V vector and 3D/video extensions to the Power ISA, implemented in a Python HDL (nMigen style)… | ||
| Shakti M-Class Libre RISC-V SoC | RISC-V Workshop Chennai 2018 | 2018-07-18 |
A 2.5 GHz RISC-V 64-bit SoC design targets a mobile-class chip with an embedded 3D GPU with 1080p decode, aiming for no backdoor coprocessors and sovereignty… | ||
| Poster / Demo Previews | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Poster session previews list concrete results and demos to see: a quantum‑resistant secure boot shows large speedups on HiFive hardware; CGEN generates… | ||
| nothing matches | ||