Shakti M-Class Libre RISC-V SoC

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" summary

A 2.5 GHz RISC-V 64-bit SoC design targets a mobile-class chip with an embedded 3D GPU with 1080p decode, aiming for no backdoor coprocessors and sovereignty. RTL publication and Libre HDL saves ~$4M in IP cost; fallback GPU is Vivante GC800 and memory option is parallel hyperRAM. Work includes an instruction-set conflict resolution (CICS) for custom extensions, auto-generating TRMs, pinmux and device trees with Python, and using Symbiotic EDA and Gallium3D/LLVM toolchains; design is funded by an anonymous sponsor and currently in active development.

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" chapters (18)

1. 0:00Introduction
2. 0:38Why do a Libre SoC
3. 2:10Good definitions
4. 4:03Does it already exist
5. 4:19Does it exist
6. 5:41Boring mundane SOC
7. 8:07Mask rights
8. 9:23Proprietary software
9. 10:44Ethical considerations
10. 12:15Interfaces
11. 13:01Comparison
12. 14:28Cost Matters
13. 14:49HyperRam
14. 15:34Video Decoding
15. 16:23RealTime Clock
16. 16:58GPU
17. 19:11Custom Extensions
18. 24:19MUX

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