Alliance / Coriolis2
summary
Coriolis2 is a hybrid C++/Python ASIC place-and-route toolchain that takes HDL (Verilog, VHDL, or Yosys RTLIL) and cell libraries and programmatically generates complete GDS-II layouts. It uses Python-based parametric, programmatic layout scripts (not a static file format or GUI) to perform placement, routing, IO ring and pad generation, and has been silicon-proven on technologies down to 180nm. The talk is a live demo walkthrough showing Coriolis2 producing a full GDS-II layout including IO pads.
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