Hardware-Aided Trusted Computing in High-Level Synthesis (HLS) for FPGAs
summary
Describes extensions and methodologies for High-Level Synthesis (HLS) compilers (from C/C++/SystemC to RTL) that add hardware-backed trusted computing features for FPGA accelerators. Covers addressing HLS-specific vulnerabilities, including side-channel weaknesses listed in the Common Weakness Enumeration (CWE), by modifying the HLS toolchain and generated RTL to produce more secure accelerators.
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