Accelerating HPC applications with Out-of-Order Commit Processors

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Describes a RISC-V hardware/software co-design that enables non-speculative out-of-order commit by having the compiler detect true branch dependencies so the core can release register file, load/store queue and other resources out of program order. Presents a lightweight new HW/OS interface for precise exception handling of out-of-order commits and evaluates the approach on C-based HPC workloads to measure performance and efficiency gains compared to conventional out-of-order cores.

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