Draft SVP64 in-place Matrix Multiply and FFT / DCT

on YouTube ↗44m

" summary

Claims an SVP64 prefix extension that runs in-place matrix multiply up to 128 FMACs with only a 3-instruction hot loop (shape setup, remap, FMAC), removing the need to transpose or spill for non-power-of-two sizes including 3x3/4x4. Demonstrates a >4× code-size drop on an MP3 inner loop and cites energy wins up to ~3.5× via reduced I-cache pressure. Implements a hardware remap finite-state machine and needs a 3-in/2-out FFT butterfly for in-place DFT/DCT; current register-file limit is 127 lanes. No new vector op instructions.

AI-written summary · about

" chapters (11)

1. 0:00Introduction to SVP64
2. 1:03Project goals and motivations
3. 3:55Matrix multiply optimization needs
4. 8:27SVP64 vectorization basics
5. 12:19General nested loop system
6. 15:53Matrix multiply instructions
7. 21:58FFT and DCT with SVP64
8. 25:51Discrete Cosine Transform challenges
9. 32:33In-place FFT implementation
10. 36:45Summary and future plans
11. 38:54Q&A session

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