Fabless SoC
summary
An academic fabless SoC named ANANTH uses the open POWER A2O core integrated with an AXI4 interconnect and Verilog RTL; peripherals implemented and functionally simulated include SPI, I2C, Ethernet MAC, NAND (2 GB) and NOR (1 GB) flash controllers, an eight‑channel DMA, a PCIe Gen3 endpoint (8 GT/s) and a working DDR3 controller. Mentor/logic simulation waveforms show AXI handshakes, page read/program sequences and PCIe/DDR transactions; design targets FPGA porting and further system‑level verification.
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chapters (11)
- 0:00Introduction to Fabless SoC
- 2:15Processor A20 Core Overview
- 5:53AXI4 On-Chip Interconnect
- 12:20Ethernet Peripheral Design
- 19:25I2C Communication Protocol
- 25:16NAND and NOR Flash Controllers
- 35:49DDR3 Memory Controller
- 39:01SPI and PCI Peripherals
- 42:55PCIe Gen 3 Implementation
- 48:41DMA Controller Design
- 53:39Project Contributors and Summary
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