Old School cache coherence-a snooping system for a multicore processor based on CVA6
summary
Project implements a low-latency snooping cache coherence unit for CVA6 cores, extending AXI to ACE over AXI and targeting quad-core use but prototyped as a dual-core FPGA prototype on a Genesys 2 with integrated L2. It runs Linux and runs Linux and plays Tetris; unit, integration and RTL litmus tests are in place. Bare-metal latency beats OpenPiton while Splash-3 on Linux trails it; current investigation targets that performance gap. Resource use <50% of OpenPiton (CPU+interconnect+LLC).
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chapters (9)
- 0:00Project motivation
- 3:24Architecture design
- 5:28Coherence control unit
- 6:52Hardware modifications
- 9:32CCU logic and operation
- 11:48Prototyping and results
- 13:50Verification strategies
- 16:59Future work and project info
- 19:22Q&A session
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