Demo: RISC-V Dual Lock-step Implementation for Safety and Security Applications

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" summary

A dual-core lockstep subsystem implements two Codasip L31 cores running identical software with a fixed or randomly jittered offset, mapped onto a Zynq-7 FPGA and instrumented with smart fault injectors that flip load/store and fetch operations; mismatches between cores trigger fault traps that a single L31 allows to corrupt navigation state. Prototype monitors instruction fetches and load/store accesses, is aimed at ASIL B qualification, plans triple voting and memory tags (Hamming/CRC8) to extend protection, and the demo shows fault detection working where single-core operation fails.

AI-written summary · about

" chapters (6)

1. 0:00Introduction to Codasip
2. 0:52Dual-core lockstep system
3. 1:34Single-core demo and faults
4. 2:50Fault injection demo
5. 3:42Lockstep demo and Q&A
6. 4:08Technical Q&A session

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