RISC-V Perf-Model: An Open Source Cycle Accurate Performance Mo...
summary
An open source, C++ Sparta discrete‑event framework underpins a trace‑driven, out‑of‑order superscalar RISC‑V perf model that ships three example cores (2‑wide, 3‑wide, 8‑wide) and cycle‑by‑cycle reporting output as text/JSON/CSV. The flow consumes STF traces from a functional run, models pipeline flow control, supports flushes, exposes modular units for swap‑in replacement, and currently uses a simple fixed‑latency memory with no branch predictor yet. A Helios visualization consumes the cycle data for pipeline debugging.
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chapters (12)
- 0:00Introduction
- 0:17Why are we doing this
- 1:43Our Charter
- 3:01RISCV PerfModel
- 4:53Sparta
- 8:17Sparta Overview
- 8:37Sparta Fragment
- 8:54Performance Model
- 9:49PerfModel Pipeline
- 11:33PerfModel Status
- 13:33PerfModel Forward
- 15:30Questions
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