Towards Open-Source and Automatic Performance Characterization Hardware

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" summary

Open-source RISC‑V cores lack the hardware hooks needed for reliable top‑down microarchitectural analysis, so an effort instruments RTL and expands event sets for RocketCore and Boom, then validates against case studies and finds HPM-based estimates off by up to a 60x discrepancy or one–two orders of magnitude. Manual RTL instrumentation takes months per core; a prototype pipeline for automated event extraction and characterization is under development to scale this work across heterogeneous SoCs.

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" chapters (7)

1. 0:00Introduction and motivation
2. 3:52Performance characterization challenges
3. 6:21Top-down micro-architectural analysis
4. 9:09Limitations of current HPM events
5. 11:37Manual implementation process
6. 13:24Future work and call for collaboration
7. 14:27Q&A session

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