Developing Custom RISC-V ISA Extensions for General Embedded Image Processing Operations

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" summary

An FPGA prototype connects a grayscale image sensor to a RISC-V ASIP that implements Custom RISC-V ISA extensions using single-instruction multiple-data (SIMD) at pixel level to compute an image histogram on-chip. The demo runs on a small IS40 FPGA at ~25 MHz, processes an image roughly every 15 seconds, and reports a 13× speedup over software while increasing prototype FPGA utilization by about 15%. Implementation details include ~4,400 loop operations and a small LUT overhead demonstrating area-optimized acceleration for embedded image preprocessing.

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