Optimizing Sparse matrix-vector multiplication on the EPAC architecture
summary
Implementation targets the EPAC Vitruvius VPU emulated on the FPGA SDV at BSC-CNS and compares CSR/CCR and ALPaC-like formats using scatter/gather versus vector permutation instructions. Using reductions inside CSR makes the vector kernel slower than scalar, but formats that avoid reductions deliver large wins: DVT512 shows >10× speed-up, other matrices range 3–6×. Results emphasize that Vitruvius VPU shuffles outperform memory gathers for these formats and that avoiding reductions is the key.
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