Improvements to RISC-V Vector code generation in LLVM

on YouTube ↗16m

" summary

LLVM adds middle-end and backend changes for RVV including VL tail folding and non-power-of-two SLP support, a pass to reduce VL to demanded, and backend tuning to avoid extra CSR switches and reduce spilling. Work uses Clang/LLVM, LLVM Exegesis and SPEC benchmarking and reports concrete gains: 12 of 16 SPEC benchmarks improve ≥5% and about 7 improve ≥10% versus Clang 18 months earlier, and LLVM is ahead of GCC on roughly 11–12 of 16.

AI-written summary · about

" chapters (9)

1. 0:00Introduction and context
2. 1:39Codegen development stages
3. 4:50RVV ISA challenges
4. 7:41Vectorization improvements
5. 9:30VL tail folding
6. 11:15Inline expansions and extensions
7. 12:40Performance improvements
8. 13:45Testing infrastructure
9. 14:46Future work and conclusion

" related talks

• 19mGetting the Most out of the LLVM Auto Vectorizer for RISC-V Vectors (RVV)Kolya Panchenko · RISC-V Summit 2022
• 18mPreview RISC-V GCC Features and Optimization Improvements for GCC-14Jeff Law · RISC-V Summit North America 2023
• 17mMaking LLVM RISC-V Compiler More Performant for EveryoneIvan Baev · RISC-V Summit North America 2023
• 24mRISC V LLVM: Towards A Production-Ready LLVM-Based ToolchainAlex Bradbury · 7th RISC-V Workshop 2017
• 17mRISC-V LLVM State of the UnionAlex Bradbury · RISC-V Summit North America 2024
• 28mLLVM for RISCVAlex Bradbury · 8th RISC-V Workshop Barcelona 2018
• 17mUnlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-VMikhail R. Gadelha · RISC-V Summit North America 2025
• 17mRecent Developments in Optimizing Compilers for RISC-VJeff Law · RISC-V Summit North America 2025