Tutorial: Spike Usage and Adding A New RISC-V Extension Support to Spike
summary
Concise how-to for adding RISC-V extensions to Spike that traces real files and build steps: sim.h/processor.h hold the vector unit, Spike models 32 vector registers and maps the spec’s seven unprivileged CSRs into six stored fields, vtype and vsetvli control element width and LMUL, and microarch is configured via the varch string which generates config.h. Instruction support follows declare_ins macros, sed-driven instruction template.cc and separate computation headers; disassembler registration and a small interactive debug helper let dumps of vector registers verify the change.
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chapters (8)
- 0:00Introduction to Spike
- 2:17Getting started with Spike
- 4:58Spike architecture overview
- 6:18Vector extension overview
- 10:31Configuring the vector unit
- 13:50Adding instructions
- 18:51Instruction disassembling
- 22:04Interactive debugging tips
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