Accelerate RISC-V Instruction Set Simulation by Tiered JIT Compilation
summary
Implements a RISC-V ISS that combines an interpreter, a fast tier-1 compiler, and an LLVM-based tier-2 compiler, claims faster interpreter performance than Spike while keeping memory use low enough for multicore simulation, and boots Linux and runs real apps. Key techniques: micro-op fusion and block chaining to cut dispatch cost, a lightweight IR plus mmap code cache with LFU replacement, and runtime tracing for hotspot classification and indirect-jump prediction. Results are promising but do not yet uniformly beat QEMU/TCG.
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chapters (8)
- 0:00RISC-V simulation challenges
- 3:41RISC-V simulator landscape
- 10:57Interpreter-first strategy
- 16:02Block chaining and micro-op fusion
- 21:09Tiered JIT architecture
- 28:11Branch prediction and translation
- 30:02Performance evaluation
- 32:10Q&A
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