Gigue: A JIT Code Binary Generator for Hardware Testing
summary
Gigue generates bare-metal JIT snapshots — self-contained RISC‑V binaries that mimic JIT code regions and exercise custom ISA extensions. It builds random methods, polymorphic inline-cache models and trampolines, emits RISC‑V assembly via the RISC‑V test framework, and validates execution with a Unicorn-based validation harness that catches exceptions and emulates custom ops. The paper adds three extensions (simple rotations, shadow-stack CFI_call/CFI_return, and domain‑tagged duplicate loads/stores), reports ~12–54 LOC to integrate each, and runs on a cycle‑accurate core simulator.
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chapters (15)
- 0:00Gigue introduction
- 1:26JIT code security challenges
- 2:51Hardware security for JIT
- 3:54RISC-V ISA for JIT
- 5:41Custom JIT instruction design
- 7:06Gigue workload motivation
- 8:10Gigue architecture
- 9:37Generating binaries with Gigue
- 11:43Sanity checks framework
- 12:46Adding custom instructions
- 13:50Testing with Unicorn
- 14:57Hardware workflow with Gigue
- 16:21Gigue use cases
- 17:04Conclusion and future work
- 18:31Q&A
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