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CHERI Performance Enhancement for a Bytecode Interpreter

Talkat VMIL 2023 · on Monday, 2023-10-23· [security, embedded-and-hardware]
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Porting MicroPython to CHERI/Morello shows actual fixes, not promises: PMCstat sampling finds 99% allocator samples on bad cases, then changing the default block size to match pointer size and raising the frame spill threshold cuts huge fragmentation-caused slowdowns. Patching the VM loop binary to work around immature LLVM back end reduces interpreter overhead further. Results: geometric-mean slowdown falls to ~1.7x (from ~5x reported), worst cases drop from ~100x to ~2x, with only ~16% extra instructions retired. change block size to pointer size patch VM loop binary

AI-written summary · about

  1. 0:00CHERI and talk intro
  2. 1:15CHERI architecture basics
  3. 8:45Performance overhead observed
  4. 10:29Memory alloc overhead causes
  5. 13:52Fixing allocator pointer sizes
  6. 16:44Adjusting spilling thresholds
  7. 18:12LLVM optim gaps in CHERI
  8. 21:28Final perf results
  9. 22:54Takeaways and future work
  10. 24:46Q&A
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